1. Field of the Invention
The present invention relates to electronics, and, in particular, to phase interpolator circuits that generate a selected phase-interpolated output clock signal from two phase-offset input clock signals.
2. Description of the Related Art
FIG. 1 shows a schematic circuit diagram of a prior-art phase interpolator 100, which receives two phase-offset input clock signals A and B and generates a phase-interpolated output clock signal Z, whose phase is interpolated between the phases of clocks A and B based on a 3-bit weighting value w. In particular, input clock signals A and B and their complements are applied at the gates of NFETs 102-108, output clock signal Z and its complement appear at nodes 110 and 112, and the three bits of weight value w and their complements are applied to the gates of (NFET) switches 114-124. Each switch is connected in series to a corresponding (NFET) current source 126-136. The sizes of the different NFETs used for the switches and current sources are such that, when the corresponding switch is turned on, the current through current source 130 is twice the current through current source 128, which is twice the current through current source 126. Similarly, the current through current source 136 is twice the current through current source 134, which is twice the current through current source 132. In addition, as shown in FIG. 1, the left side of phase interpolator 100 has an additional transistor pair consisting of switch 138 and current source 140, which is always on (due to the gate of switch 138 being connected to Vdd). The current through this additional transistor pair is selected to achieve the results shown in Table I.
Table I shows the different phases of output clock Z for different weighting values w when input clocks A and B are offset by 90 degrees (in particular, when the phase of clock A is 0 degrees, and the phase of clock B is 90 degrees). Greater numbers of different interpolated phase values between 0 and 90 degrees can be achieved by connecting additional, appropriately sized switch/current source pairs on each side of phase interpolator 100 and using weight values having a corresponding additional number of bits.
TABLE IPRIOR-ART OUTPUT PHASESw[2]w[1]w[0]Output phase (degrees)000000111.2501022.501133.751004510156.2511067.511178.75
FIG. 2 shows a plot of the amplitude of output clock Z of FIG. 1 for different output phases between 0 and 90 degrees, normalized for 0 degrees (i.e., where output clock signal Z is based entirely on input clock A) and at 90 degrees (i.e., where output clock Z is based entirely on input clock B). As shown in FIG. 2, the output amplitude drops by almost 30% at a 45-degree interpolated phase angle. This amplitude variation with interpolation angle can result in errors in downstream circuitry that relies on phase-interpolated output clock Z for its processing.